1. Field of Invention
The present invention relates to a method of manufacturing a semiconductor device, particularly to a semiconductor device including a memory cell region and peripheral circuit region, the peripheral circuit region having a high-voltage transistor and a low-voltage transistor.
2. Description of the Related Art
Among semiconductor devices, a typical nonvolatile memory such as a NAND flash memory includes a memory cell and a peripheral circuit cell. The memory cell is driven by the peripheral circuit cell and is provided with a low-voltage transistor. The peripheral circuit cell, on the other hand, is generally provided with both types of high- and low-voltage transistors of p-type and n-type respectively.
Impurities are doped into a semiconductor substrate by way of ion implantation to form a source/drain region for each transistor. At this time, in the case of a high-voltage transistor having a thick gate insulating film, the gate insulating film formed on the semiconductor substrate surface needs to be removed upon ion implantation. The gate insulating film formed an the impurity diffusion region is removed by patterning a resist by lithography process.
On the other hand, the low-voltage transistor has a thin gate insulating film. Therefore, in the ion implantation process for forming the source/drain region, a predetermined diffusion region can be formed by implanting ions without removing the gate insulating film formed on the semiconductor substrate surface. A complimentary metal oxide semiconductor integrated circuit (CMOSIC) technology using the above process is disclosed in JP-A-H08-125031.
In the above described conventional manufacturing method, the process to remove the gate insulating film in the high- and low-voltage transistors respectively is performed separately. This is due to difference in the film thickness of the respective transistors. That is, in case the gate insulating films are removed simultaneously, because the low-voltage transistor has a thinner gate insulating film, the gate insulating film of the low-voltage transistor is etched away before the high-voltage transistor exposes the underlying silicon substrate surface.
In such case, it is not possible to selectively etch the gate insulating film alone by an anisotropic etch process such as RIE (Reactive Ion Etching) process. Therefore, even if the etch process is performed with a higher selective ratio in relative to silicon; the silicon substrate surface still becomes etched. Due to the electrical characteristic of a transistor, such configuration results in adverse effects such as a short channel effect. Thus, the process of removing the gate insulating films of different thickness need to be carried out separately, thereby not being able to reduce the times of lithography process.